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lib/systems/architectures: Define inferiors for common ARM64 CPUs
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@@ -339,134 +339,161 @@ rec {
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};
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# a superior CPU has all the features of an inferior and is able to build and test code for it
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inferiors = {
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# x86_64 Generic
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default = [ ];
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x86-64 = [ ];
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x86-64-v2 = [ "x86-64" ];
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x86-64-v3 = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
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x86-64-v4 = [ "x86-64-v3" ] ++ inferiors.x86-64-v3;
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inferiors =
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let
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withInferiors = archs: lib.unique (archs ++ lib.flatten (lib.attrVals archs inferiors));
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in
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{
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# x86_64 Generic
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default = [ ];
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x86-64 = [ ];
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x86-64-v2 = [ "x86-64" ];
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x86-64-v3 = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
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x86-64-v4 = [ "x86-64-v3" ] ++ inferiors.x86-64-v3;
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# x86_64 Intel
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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nehalem = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
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westmere = [ "nehalem" ] ++ inferiors.nehalem;
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sandybridge = [ "westmere" ] ++ inferiors.westmere;
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ivybridge = [ "sandybridge" ] ++ inferiors.sandybridge;
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# x86_64 Intel
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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nehalem = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
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westmere = [ "nehalem" ] ++ inferiors.nehalem;
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sandybridge = [ "westmere" ] ++ inferiors.westmere;
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ivybridge = [ "sandybridge" ] ++ inferiors.sandybridge;
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haswell = lib.unique (
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[
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"ivybridge"
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"x86-64-v3"
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]
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++ inferiors.ivybridge
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++ inferiors.x86-64-v3
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);
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broadwell = [ "haswell" ] ++ inferiors.haswell;
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skylake = [ "broadwell" ] ++ inferiors.broadwell;
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haswell = lib.unique (
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[
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"ivybridge"
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"x86-64-v3"
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]
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++ inferiors.ivybridge
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++ inferiors.x86-64-v3
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);
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broadwell = [ "haswell" ] ++ inferiors.haswell;
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skylake = [ "broadwell" ] ++ inferiors.broadwell;
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skylake-avx512 = lib.unique (
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[
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"skylake"
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"x86-64-v4"
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]
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++ inferiors.skylake
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++ inferiors.x86-64-v4
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);
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cannonlake = [ "skylake-avx512" ] ++ inferiors.skylake-avx512;
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icelake-client = [ "cannonlake" ] ++ inferiors.cannonlake;
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icelake-server = [ "icelake-client" ] ++ inferiors.icelake-client;
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cascadelake = [ "cannonlake" ] ++ inferiors.cannonlake;
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cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake;
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tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server;
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sapphirerapids = [ "tigerlake" ] ++ inferiors.tigerlake;
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emeraldrapids = [ "sapphirerapids" ] ++ inferiors.sapphirerapids;
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skylake-avx512 = lib.unique (
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[
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"skylake"
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"x86-64-v4"
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]
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++ inferiors.skylake
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++ inferiors.x86-64-v4
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);
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cannonlake = [ "skylake-avx512" ] ++ inferiors.skylake-avx512;
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icelake-client = [ "cannonlake" ] ++ inferiors.cannonlake;
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icelake-server = [ "icelake-client" ] ++ inferiors.icelake-client;
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cascadelake = [ "cannonlake" ] ++ inferiors.cannonlake;
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cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake;
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tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server;
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sapphirerapids = [ "tigerlake" ] ++ inferiors.tigerlake;
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emeraldrapids = [ "sapphirerapids" ] ++ inferiors.sapphirerapids;
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# CX16 does not exist on alderlake, while it does on nearly all other intel CPUs
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alderlake = [ ];
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sierraforest = [ "alderlake" ] ++ inferiors.alderlake;
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# CX16 does not exist on alderlake, while it does on nearly all other intel CPUs
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alderlake = [ ];
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sierraforest = [ "alderlake" ] ++ inferiors.alderlake;
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# x86_64 AMD
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# TODO: fill this (need testing)
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btver1 = [ ];
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btver2 = [ ];
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bdver1 = [ ];
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bdver2 = [ ];
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bdver3 = [ ];
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bdver4 = [ ];
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# Regarding `skylake` as inferior of `znver1`, there are reports of
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# successful usage by Gentoo users and Phoronix benchmarking of different
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# `-march` targets.
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#
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# The GCC documentation on extensions used and wikichip documentation
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# regarding supperted extensions on znver1 and skylake was used to create
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# this partial order.
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#
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# Note:
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#
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# - The successors of `skylake` (`cannonlake`, `icelake`, etc) use `avx512`
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# which no current AMD Zen michroarch support.
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# - `znver1` uses `ABM`, `CLZERO`, `CX16`, `MWAITX`, and `SSE4A` which no
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# current Intel microarch support.
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#
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# https://www.phoronix.com/scan.php?page=article&item=amd-znver3-gcc11&num=1
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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# https://en.wikichip.org/wiki/amd/microarchitectures/zen
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# https://en.wikichip.org/wiki/intel/microarchitectures/skylake
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znver1 = [ "skylake" ] ++ inferiors.skylake; # Includes haswell and x86-64-v3
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znver2 = [ "znver1" ] ++ inferiors.znver1;
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znver3 = [ "znver2" ] ++ inferiors.znver2;
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znver4 = lib.unique (
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[
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"znver3"
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"x86-64-v4"
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]
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++ inferiors.znver3
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++ inferiors.x86-64-v4
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);
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znver5 = [ "znver4" ] ++ inferiors.znver4;
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# x86_64 AMD
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# TODO: fill this (need testing)
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btver1 = [ ];
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btver2 = [ ];
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bdver1 = [ ];
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bdver2 = [ ];
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bdver3 = [ ];
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bdver4 = [ ];
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# Regarding `skylake` as inferior of `znver1`, there are reports of
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# successful usage by Gentoo users and Phoronix benchmarking of different
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# `-march` targets.
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#
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# The GCC documentation on extensions used and wikichip documentation
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# regarding supperted extensions on znver1 and skylake was used to create
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# this partial order.
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#
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# Note:
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#
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# - The successors of `skylake` (`cannonlake`, `icelake`, etc) use `avx512`
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# which no current AMD Zen michroarch support.
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# - `znver1` uses `ABM`, `CLZERO`, `CX16`, `MWAITX`, and `SSE4A` which no
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# current Intel microarch support.
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#
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# https://www.phoronix.com/scan.php?page=article&item=amd-znver3-gcc11&num=1
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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# https://en.wikichip.org/wiki/amd/microarchitectures/zen
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# https://en.wikichip.org/wiki/intel/microarchitectures/skylake
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znver1 = [ "skylake" ] ++ inferiors.skylake; # Includes haswell and x86-64-v3
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znver2 = [ "znver1" ] ++ inferiors.znver1;
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znver3 = [ "znver2" ] ++ inferiors.znver2;
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znver4 = lib.unique (
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[
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"znver3"
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"x86-64-v4"
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]
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++ inferiors.znver3
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++ inferiors.x86-64-v4
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);
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znver5 = [ "znver4" ] ++ inferiors.znver4;
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# ARM64 (AArch64)
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armv8-a = [ ];
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"armv8.1-a" = [ "armv8-a" ];
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"armv8.2-a" = [ "armv8.1-a" ] ++ inferiors."armv8.1-a";
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"armv8.3-a" = [ "armv8.2-a" ] ++ inferiors."armv8.2-a";
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"armv8.4-a" = [ "armv8.3-a" ] ++ inferiors."armv8.3-a";
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"armv8.5-a" = [ "armv8.4-a" ] ++ inferiors."armv8.4-a";
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"armv8.6-a" = [ "armv8.5-a" ] ++ inferiors."armv8.5-a";
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"armv8.7-a" = [ "armv8.6-a" ] ++ inferiors."armv8.6-a";
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"armv8.8-a" = [ "armv8.7-a" ] ++ inferiors."armv8.7-a";
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"armv8.9-a" = [ "armv8.8-a" ] ++ inferiors."armv8.8-a";
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armv9-a = [ "armv8.5-a" ] ++ inferiors."armv8.5-a";
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"armv9.1-a" = [
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"armv9-a"
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"armv8.6-a"
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] ++ inferiors."armv8.6-a";
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"armv9.2-a" = lib.unique (
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[
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"armv9.1-a"
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"armv8.7-a"
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]
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++ inferiors."armv9.1-a"
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++ inferiors."armv8.7-a"
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);
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"armv9.3-a" = lib.unique (
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[
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"armv9.2-a"
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"armv8.8-a"
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]
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++ inferiors."armv9.2-a"
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++ inferiors."armv8.8-a"
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);
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"armv9.4-a" = [ "armv9.3-a" ] ++ inferiors."armv9.3-a";
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# ARM64 (AArch64)
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armv8-a = [ ];
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"armv8.1-a" = [ "armv8-a" ];
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"armv8.2-a" = [ "armv8.1-a" ] ++ inferiors."armv8.1-a";
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"armv8.3-a" = [ "armv8.2-a" ] ++ inferiors."armv8.2-a";
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"armv8.4-a" = [ "armv8.3-a" ] ++ inferiors."armv8.3-a";
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"armv8.5-a" = [ "armv8.4-a" ] ++ inferiors."armv8.4-a";
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"armv8.6-a" = [ "armv8.5-a" ] ++ inferiors."armv8.5-a";
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"armv8.7-a" = [ "armv8.6-a" ] ++ inferiors."armv8.6-a";
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"armv8.8-a" = [ "armv8.7-a" ] ++ inferiors."armv8.7-a";
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"armv8.9-a" = [ "armv8.8-a" ] ++ inferiors."armv8.8-a";
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armv9-a = [ "armv8.5-a" ] ++ inferiors."armv8.5-a";
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"armv9.1-a" = [
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"armv9-a"
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"armv8.6-a"
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] ++ inferiors."armv8.6-a";
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"armv9.2-a" = lib.unique (
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[
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"armv9.1-a"
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"armv8.7-a"
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]
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++ inferiors."armv9.1-a"
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++ inferiors."armv8.7-a"
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);
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"armv9.3-a" = lib.unique (
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[
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"armv9.2-a"
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"armv8.8-a"
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]
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++ inferiors."armv9.2-a"
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++ inferiors."armv8.8-a"
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);
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"armv9.4-a" = [ "armv9.3-a" ] ++ inferiors."armv9.3-a";
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# other
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armv5te = [ ];
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armv6 = [ ];
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armv7-a = [ ];
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mips32 = [ ];
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loongson2f = [ ];
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};
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# ARM
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cortex-a53 = [ "armv8-a" ];
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cortex-a72 = [ "armv8-a" ];
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cortex-a55 = [
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"armv8.2-a"
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"cortex-a53"
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"cortex-a72"
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] ++ inferiors."armv8.2-a";
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cortex-a76 = [
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"armv8.2-a"
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"cortex-a53"
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"cortex-a72"
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] ++ inferiors."armv8.2-a";
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# Ampere
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ampere1 = withInferiors [
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"armv8.6-a"
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"cortex-a55"
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"cortex-a76"
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];
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ampere1a = [ "ampere1" ] ++ inferiors.ampere1;
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ampere1b = [ "ampere1a" ] ++ inferiors.ampere1a;
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# other
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armv5te = [ ];
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armv6 = [ ];
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armv7-a = [ ];
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mips32 = [ ];
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loongson2f = [ ];
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};
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predicates =
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let
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